A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having electric fuses to be electrically broken.
B) Description of the Related Art
Electric fuses formed on a semiconductor substrate are used for redundancy of RAM and identification of chip IDs. An electric fuse is broken by applying large current thereto and generating electromigration. An electric fuse is characterized by a smaller occupying area than that of a fuse to be broken by laser irradiation. A fuse to be broken by laser appropriates all wiring layers for its own use, whereas an electric fuse uses only one wiring layer. The electric fuse causes a high degree of freedom in layout. Test, break, and break check can be performed by using a tester. Therefore, as compared to break by laser, a test cost can be reduced. The electric fuse can be broken even after packaging.
FIG. 9 is an equivalent circuit of an electric fuse and its breaker circuit adopted in a conventional semiconductor integrated circuit. A similar breaker circuit is disclosed in ISSCC 2004 3.7 Power PC 970 in 130 nm and 90 nm Technologies.
One terminal of an electric fuse 1 is connected to the drain region of a breaker transistor T1. The source region of the breaker transistor T1 is grounded. The other terminal of the electric fuse 1 is connected to a breaker pad 2. The terminal connected to the breaker pad 2 is grounded via a first read transistor T2. The terminal of the electric fuse 1 connected to the breaker transistor T1 is connected to a fuse information read circuit 8 via a second read transistor T3. The breaker transistor T1, first read transistor T2 and second read transistor T3 respectively connected directly to the electric fuse 1 consists of high breakdown voltage transistors capable of being durable for high voltage during breaking the fuse. A ground potential VSS is applied to a p-type well in which the breaker transistor T1 and read transistors T2 and T3 are disposed.
When the electric fuse 1 is to be broken, the read transistors T2 and T3 are turned off and the breaker transistor T1 is turned on to apply a fusing current to a serial circuit of the electric fuse 1 and breaker transistor T1 from the breaker pad 2. For reading whether the electric fuse 1 is a breakdown state or a non-breakdown state, the read transistors T2 and T3 are turned on and the breaker transistor T1 is turned off. The fuse information read circuit 8 reads the state of the electric fuse 1 and outputs a read result to an output terminal VF.
FIG. 10 shows a breaker circuit of an electric fuse disclosed in JP-A-SHO 59-66142. A pad 71 is connected to one terminal of a serial circuit of an electric fuse 75 and a breaker transistor TR1 on the side of the electric fuse 75, and the source region of the breaker transistor TR1 is grounded. A substrate potential of the breaker transistor TR1 is supplied from a pad 70 having the same potential as that of the semiconductor substrate.
An electronic circuit 72 is formed on the same substrate. The electronic circuit 72 includes an NMOS transistor TR2. The substrate potential of the NMOS transistor TR2 is also applied from the pad 70. An interconnection point between the electric fuse 75 and pad 71 is connected to the gate electrode of the NMOS transistor TR2.
When the electric fuse 75 is to be broken, the breaker transistor TR1 is turned on and a power supply voltage is applied to the pad 71 to apply a fusing current to the electric fuse 75. In order to confirm the state of the electric fuse 75 after it is broken, the pad 70 is maintained at a lower potential than that of the pad 71. If the electric fuse 75 is not broken, a forward current flows across a pn-junction between the diffusion layer of the breaker transistor TR1 and the semiconductor substrate. If the electric fuse 75 is broken, this forward current will not flow.
If the pad 71 is connected to the source or drain region of the NMOS transistor in the electronic circuit 72, a forward current flows across the pn-junction between the diffusion layer of the NMOS transistor and the semiconductor substrate while the breakdown state of the electric fuse 75 is confirmed. It is not possible therefore to confirm the breakdown state of the electric fuse 75. In the circuit shown in FIG. 10, since the pad 71 is connected only to the gate electrode of the NMOS transistor TR2 in the electronic circuit 72, current will not flow from the pad 70 to the pad 71 via the NMOS transistor in the electronic circuit 72.